Job Description

Job Responsibilities: * Responsible for all the aspects of the ASIC front end design, including the micro- architecture, RTL, synthesis, logic and timing verification. * Document, execute the pl Job Responsibilities: Responsible for all the aspects of the ASIC front end design, including the micro- architecture, RTL, synthesis, logic and timing verification. Document, execute the plan, and deliver fully verified, high performance, area and power efficient design to achieve the targets and specifications. Work with the verification team, guide and review the verification plan. Participate in post silicon bring-up and validation. Salary: $7,000 - $14,000 + AWS + VB (Depends on employee & company's performance) Working Hours: Mon - Fri, 9am - 6pm Period: Permanent Location: Ubi Requirements: 210 years of complex high-speed digital IC design experience with all stages in the ASIC design flow, DFT, Synthesis, timing analysis, ECO, bring up & lab debug. Bachelor's degree in Electrical Engineering or Computer Engineer or related field required MS or Ph.D. degree a plus. Experience with standard EDA tools from Synopsys or Cadence. Strong working knowledge of languages relevant to the ASIC development process including Verilog, Unix/Perl Scripting or Python, and C/C++. Experiences with complex networking ASIC design and knowledge with networking protocols and RFCs are big plusses. Good Team work In lieu of physical interviews, we will be conducting virtual interview, i.e. Skype/WhatsApp/Facetime/Zoom Interested applicants, kindly email your detailed resume (MS Word format is preferred): [HIDDEN TEXT] (Registration no: R21100797) Please ensure that applications sent through email are no bigger than 1Mb. We thank all applicants for your interest but regret to inform that only shortlisted candidates would be notified. Success Human Resource Centre Pte Ltd (EA License Number: 97C4832) 3 Shenton Way, #19-01 Shenton House, Singapore 068805 T: 6337 3183 | F: 6337 0329 | W: www.successhrc.com.sg