Job Description

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The Opportunity:

• Permanent role
• Work Location: North-east
• Work Hour: 8am - 5pm

Adecco is partnering with a renowned Semiconductor Equipment Manufacturer who specialize in Wafer Inspection and Metrology Equipmenton hiring an Algorithm Engineer. This position will report under a new R&D team and will be responsible for FPGA design for new systems as well as sustaining support for manufacturing and customer escalations.
The Job:

• Designing, implementing, and debugging of FPGAs for sensing and communications systems (cameras, sensors, motors etc.)
• Collaborate with cross functional team members to design FPGA Firmware for high-performance mixed-signal systems and solve complex technical challenges
• Develop complex, high-speed, innovative FPGA-based designs including design, verification, simulations, synthesis, place and route, and timing closure.
• Responsible for RTL design and verification, as well as hardware bring-up and debug FPGA for motion control, sensing and imaging systems.
• Optimize FPGA designs for the area, speed, and power to meet system requirements; analyze architectural trade-offs and validate for system sample rate and latency.
• Participate in all phases of FPGA design flow, define FPGA design requirement specifications and develop design projects from concept design to wafer inspection tool production release
• Understand and capture the project specifications and performance requirements on board and system level. Adhere to project timelines and deliverables
• Write technical documentation that meets the defined quality standards as required

The Talent:

• Hands on experience with complex FPGA design (Xilinx preferred), FPGA simulation, and FPGA timing analysis
• Proficiency in Verilog or System Verilog
• Proficiency in FPGA simulation tools such as VCS, Modelsim/Questasim or equivalent
• Proficiency in FPGA design tools such as Vivado or equivalent
• Hands on experience with lab equipment such as logic analyzer, oscilloscope
• Solid knowledge of various protocols to interface different peripherals: PCIe, Ethernet, CSSI, DDR4, 10G, SPI, I2C, etc.
• Understand FPGA timing analysis and be enable to solve timing related issues
• Understanding of clock domain crossing (CDC) techniques
• Hands on experience with lab equipment such as logic analyzer, oscilloscope
• Solid knowledge of various protocols to interface different peripherals: PCIe, Aurora, DDR4, 10G, SPI, I2C, etc.
• Solid Knowledge of networking and Embedded Linux build systems

Next Steps:

• Prepare your updated resume (please include your current salary package with a full breakdown such as base, incentives, annual wage supplement, etc.) and expected package.
• Apply through this application or send your resume to huiyang.loo@adecco.com in MS Word Copy. We'd love to hear from you!
• We regret that only shortlisted candidates will be notified.

Loo Hui Yang
Direct Line: 9342 5045
EA License No: 91C2918
Personnel Registration Number: R11011456