Own the full lifecycle of PDE technology pillars, including roadmap definition, execution, and closure. Define technical objectives, key deliverables, and resource allocation for pillar initiatives. Lead cross-functional engineering teams across TD, HVM, CPI, DRAM, and NPI to achieve aggressive technology milestones. Bachelor's or Master's degree in Engineering, Materials Science, or related technical discipline. 8+ years of experience in semiconductor packaging, process integration, or technology development. Proven ability to lead complex, cross-functional technical programs in a high-tech environment. Deep understanding of advanced packaging flows including hybrid bonding, CoWoS, and chiplet integration. Strong technical communication and leadership skills. Expertise in simulation modeling, yield enhancement, and defectivity analysis. Develop and enforce standardized methodologies for technical program management and pillar governance. Ensure compliance with internal governance models and customer technical requirements. Facilitate technical communication across BU, PDT, TPM, and central engineering teams. Provide leadership updates on technical progress, risks, and mitigation strategies. Performance & Continuous Improvement
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