Job Description

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Lead physical implementation at both block and top levels, including floorplanning, placement, clock tree synthesis (CTS), and routing; Drive timing closure, formal verification, low-power analysis, and power optimization; Perform IR drop and electromigration (EM) analysis, as well as physical verification including DRC, LVS, and ESD checks; Support cross-functional integration and validation between frontend and backend design teams; Contribute to the development and refinement of backend flows for advanced process technologies. Requirements:


Master's degree or higher in Microelectronics, IC Design, Electrical Engineering, Computer Engineering, or a related field; 5-10+ years of hands-on experience in digital backend design for ASIC or SoC products; Proven experience with advanced technology nodes such as 3nm, 4nm, or 6nm, with successful tape-out records; Strong background working with major foundries such as TSMC or Samsung at either block-level or full-chip scale; Proficient with industry-standard EDA tools, including Cadence and/or Synopsys platforms for P&R, STA, and physical verification; Deep expertise across the full backend flow--from netlist to GDSII--including floorplanning, power planning, placement, optimization, CTS, routing, ECO implementation, RC/SPEF extraction, and STA sign-off; Solid grasp of static timing analysis and low-power design techniques (e.g., multi-VDD, power domains, UPF); Experience with complex SoC projects; familiarity with high-speed modules such as CPU, DDR, or SerDes is a strong advantage; Proficient in automation and scripting using languages such as Tcl, Perl, or Shell; * Strong communication skills and a collaborative mindset, with the ability to work effectively in cross-functional teams.