Job Description

Key Job Responsibilities:

Develop and optimize electroplating, seed etching, and PR stripping processes Design and improve processes for TSV, RDL, Cu pillar, and micro bump formation Evaluate and introduce new materials and equipment for plating/etching process integration Conduct pre-production process validation and yield stabilization Perform DOE planning and analyze experimental data using statistical tools (e.g.,SPC, Minitab, JMP) Develop customized processes and provide technical support for customer programs Set up equipment and optimize operating conditions in coordination with vendors Troubleshoot quality issues across plating and etching processes Support development of advanced packaging technologies including 2.5D, fan-out, and SiP

Qualifications:

Bachelor's degree or higher in Engineering or Science (e.g., Materials Science, Chemistry, Chemical Engineering, Electronics, Advanced Materials) Minimum 3 years of hands-on experience in plating, etching, or stripping processes in semiconductor manufacturing Fundamental understanding of advanced semiconductor fabrication and integration processes Strong skills in experiment design, statistical data analysis (e.g., SPC, Minitab, JMP), and technical reporting Proficiency in preparing technical documentation and delivering presentations Ability to communicate technical content clearly in English (written and verbal) Basic knowledge of semiconductor process equipment and materials Experience in key back-end processes such as TSV, RDL, and micro bump Knowledge of advanced packaging technologies including 2.5D, fan-out, and flip-chip Familiarity with related processes such as photo, chip attach, and underfill Proven experience in joint development projects with global customers Hands-on collaboration with material or equipment suppliers for co-evaluation or integration Expertise in process reliability testing (e.g., thermal cycling, HAST) Experience in process automation or smart fab environments Working proficiency in tools such as AutoCAD or ANSYS * In-depth understanding of etch/strip conditions for back-end photoresist materials