Job Description

Job Responsibilities: * Define SOC/IP design architecture according to product spec. * Deliver RTL design according to project requirements, meeting milestone and corresponding quality check. Job Responsibilities: Define SOC/IP design architecture according to product spec. Deliver RTL design according to project requirements, meeting milestone and corresponding quality check. SOC design flow and methodology development. Support DFT, verification and implementation tasks for design debug/improvement. Support FPGA tasks such as emulation, validation and debugging. Chip bring up support. Period: Permanent Working Hours: Office hours (Monday to Friday, 9-6pm) Salary: $7,000 - $14,000 Location: Ubi Requirements: 6 years BS in Electrical/ Electronic Engineering or 3 years MS preferred. Skilled with Verilog, System Verilog programming experience with simulation, synthesis and timing. Tapeout experience is plus. Familiar with SoC architecture, bus matrix (AMBA, NOC,etc), low power, clock/reset design and IP integration. Familiar with lint, CDC, UPF, synthesis and STA flow knowledge with DFT is plus. Experience or knowledges with high-speed interface development such as mipi, PCIE and DDR is plus. Experience and knowledges of ARM Cortex cores, Tensilica DSPs, Trustzone and security engine is plus. Interested applicants, kindly email your detailed resume (MS Word format is preferred): [HIDDEN TEXT] (Registration no: R2092012 ) Please ensure that applications sent through email are no bigger than 1Mb. We thank all applicants for your interest but regret to inform that only shortlisted candidates would be notified. Success Human Resource Centre Pte Ltd (EA License Number: 97C4832) 3 Shenton Way, #19-01 Shenton House, Singapore 068805 T: 6337 3183 | F: 6337 0329 | W: www.successhrc.com.sg