Job Description

Responsibilities:

Lead mixed-signal subsystem design from implementation through to final delivery for chip-level integration. Perform micro-architectural studies to identify and implement optimal hardware solutions for IP digital blocks in line with product requirements. Develop RTL logic modules using Verilog HDL, including (but not limited to) power and clock management units, IP subsystems, high-speed digital design, analog/digital interfaces, accelerators, and filters. Ensure all required design and process documentation is prepared and maintained according to established quality standards. Conduct and facilitate design and verification reviews with technical teams across the project lifecycle. Perform logic synthesis, timing closure, and power analysis to optimize RTL designs for performance and efficiency. Execute pre-silicon verification using multiple methodologies, such as: Constrained-random verification with UVM test benches at block, subsystem, and chip level SPICE co-simulation for mixed-signal validation FPGA-based emulation for system-level testing.

Requirements:

Engineering Degree in relevant field. Hands-on experience in RTL design and verification. Minimum 6 Years of experience,strong background in VLSI design, including RTL programming, logic synthesis, timing/power optimization, and pre-silicon verification methodologies. * Familiarity with industry-standard EDA tools, simulation environments, and design/verification best practices.