Job Description

Lead the development and execution of Wireless SoC\xe2\x80\x99s from definition, through execution, and into production Definition and Planning

• Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates.

• Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse.

• Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies.

Project Execution Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation. Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure. Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams. Follow established quality procedures and processes to achieve first tapeout. Validation to Production Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification. Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary Requirements: Relevant Engineering Degree with a minimum of 10 years of related experience. Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus. Top-down planning and execution of SOC projects. Experience in full-chip development cycle Hands-on experience in architecture, micro-architecture, digital design processes Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. Knowledge of processors like RISC-V and ARM processors Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, ATPG, MBIST Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) Knowledge of scripting languages like Perl, Python, Tcl, shell