Job Description

[What you will do] You will be in a energetic team working on advanced technology development, as the pioneer to setup leading edge design platform for MediaTek multi-vertical projects. o Develop complex circuit block, test key for leading-edge process node (planar, finfet, nanosheet) from schematic netlist to gds. o Develop standard cell library from architecture evaluation, PPA assessment and customized cell design with different PPA purpose and IP blocks. o Work with layout engineer for design implementation and physical verification including DRC/LVS/ERC/ANT. o Perform layout extraction, simulation, analyze simulation data, including performance, power, leakage, for layout dependent effect study. o Work with digital team and testing team for design implementation and chip level silicon data collection. o Develop processing flow for silicon data analysis, visualization, AI model regression. o Develop advanced library generation methodology and flow, including characterization, kit generation, regression, and quality assurance. o Perform timing/power/constraint/noise/LVF variation characterization for standard cell or complex circuit blocks. o Work with circuit designer and tool vendors to tackle modelling difficulties, like accuracy and runtime issues, especially for complex circuit blocks. o Responsible for new kits enablement and evaluation, like EM characterization, aging characterization. o Involve with data analysis and machine learning as well for circuit performance and power assessment. #LI-WC1

[What you bring] o BS/MS in Electrical and Electronic Engineering/Computer Engineering/Computer Science with minimum 3 years(MS) or 5 years(BS) industry experience. (We have entry level position with the same function, no prior experience is required.) o Familiar with Python, Perl, Tcl or C/C++ for flow development and data analysis, machine learning. o Basic knowledge of digital design and/or circuit design. o Solid understanding of foundation IP design, with device physics, transistor level circuit, layout dependent effect knowledge. o Experience of test chip design in FinFet/Nanosheet technologies is a plus, with understanding of DRM, layout rules, PV check, and simulation skills. o Strong communication and teamwork skills to collaborate effectively with cross-functional teams.