Validation Engineer Job in J P INFOTEC PTE. LTD.

Validation Engineer

SG, Singapore

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Job Description

Si Validation Engineer :

Programming language - C & Python Good Understanding of SOC architectures and validation of Integrated IP's Test plan development and test content writing based on design specifications, architecture document & end use case scenarios for SOC's Silicon bring up, initial power-on, bootup & functional testing Preferred Memory & PCIE validation experience Virtualization as added advantage Knowledge of RocM framework Debug and root cause analysis for complex SOC's in post Silicon test phase. * Automation and test infrastructure development for automated testing post power-on

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