UNI CONNECT

Job Description : Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system on chip (SoC) Full Chip Static Timing Analysis. Define and own full chip timing constraint creation and validation,…

Job Description : Lead, drive and execute Standard cell characterization, QA flows and its methodology development, deliver library view generation to enable digital, analog and mixed signal design and PnR flows Characterize and optimize standard cell libraries for FinFET technology,…

Job Description : Participate in mix signal IC product design: Chip/block level RTL design and implementation. Design signal processing blocks from algorithm, convert Algorithms to digital design. Architecture definition according to product spec. Participate in block and chip level verification:…