Job Description

Job Responsibilities: * In this role, you will work with our analog design engineers to layout the high speed, high performance analog circuit such as: high speed and low power ADC, high linearity Job Responsibilities: In this role, you will work with our analog design engineers to layout the high speed, high performance analog circuit such as: high speed and low power ADC, high linearity and low noise amplifier, high linearity and low noise analog filter high performance PLL, low noise OSC, high speed SERDES, inductive or capacitive base power converter, low noise LDO, high performance temperature sensor, low noise and high accuracy voltage/current reference etc. Engage in floor planning, die size estimates, block level routing and top level chip assembly. Apply high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electro-migration. Demonstrate your experience with analog layout for silicon chips in mass production. Read and interpret Design Rule Manuals. Perform physical layout implementation at block and top levels utilizing best practices for matching, shielding, dummies, fills, and isolation. Period: Permanent Working Hours: Office hours (Monday to Friday, 9-6pm) Salary: $7,000 - $14,000 Location: Ubi Requirements: BS in Electrical engineering or equivalent, 5 years or more of CMOS analog circuit layout experience. Ability to layout analog circuitry in a size/time-constrained environment. Understand how to optimize layout to reduce parasitic effect in high speed analog circuit. Understand device matching techniques such as common centroid, matching, and the use of dummy devices, etc. Understand signal conditioning/protection techniques such as shielding, isolation, etc. Understand ESD and Latch-up issues and have experience in good layout practice to prevent ESD and Latch-up issues. Ability to solve design problems while using a combination of technical skills, intuition, and creativity. Proficiency in floor planning activities with block level and top level assembly/routing. LVS troubleshooting and debugging skills. Excellent collaboration skills including written and verbal communication. Much have layout Experience in 28nm or 40nm and experience in FinFET is preferred. Interested applicants, kindly email your detailed resume (MS Word format is preferred): [HIDDEN TEXT] (Registration no: R2092012 ) Please ensure that applications sent through email are no bigger than 1Mb. We thank all applicants for your interest but regret to inform that only shortlisted candidates would be notified. Success Human Resource Centre Pte Ltd (EA License Number: 97C4832) 3 Shenton Way, #19-01 Shenton House, Singapore 068805 T: 6337 3183 | F: 6337 0329 | W: www.successhrc.com.sg