Functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, RTL and gate verification, synthesis script and silicon validation.
Participate in co-development activities to help prototype ASIC designs in FPGA or other software models to support pre-silicon firmware development and verification.
Requirements
:
BS or MS degree in electrical engineering or equivalent with at least 2 years IC design experience
Familiar with digital ASIC/SOC design flow from RTL to silicon characterization
Knowledge of digital circuit design, embedded system design, verification, and product development lifecycle
Deep understanding of how RTL code impacts area, power, and operating frequency, as well as the requirements for timing, power, and area optimization in synthesis implementation, along with the associated script files such as SDC and UPF.
Familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.
Familiar with UVM verification methodology.
Familiar with design and programming languages: Verilog, System Verilog, Python, Perl, C, C++, etc.
* Deep knowledge and domain know-hows in ARM/RISC-V microprocessor subsystem
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