Job Description

Key Responsibilities:

Responsible for the IC Design in development and quality control of workflows related to logic synthesis, formal verification, and timing analysis. Assist the front-end design team in preparing module-level timing constraints; complete full-chip flattened SDC creation and quality checks in collaboration with the front-end team. Execute the full-chip STA (Static Timing Analysis) process, perform full-chip timing ECOs, and carry out related timing analysis tasks.

Requirements:

Bachelor's degree or above in Electrical Engineering, Computer Engineering, or related fields, with at least 3 years of relevant working experience. Candidates with over 10 years of related experience will be considered for a senior position. Proficient in Verilog language, with solid knowledge of synthesis flow, full-chip synthesis strategies, and debugging skills in formal verification. Strong understanding and hands-on experience with SDC; familiar with methodologies for full-chip timing analysis and optimization. Skilled in using various EDA tools for synthesis, formal verification, and static timing analysis. Proficiency in scripting languages such as Tcl, Perl, and Python is highly preferred. Familiar with DFT (Design for Testability) concepts and methods such as BIST, SCAN, JTAG, and ATPG is an advantage. Self-motivated, and a good team player with excellent collaboration spirit.



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