Engineer / Senior Engineer (design Verification) [spd3/campus'23]
Singapore, Singapore
Job Description
- IP/SOC design verification in Networking, AI, Wifi, 5G, AR/VR
- Low Power verification
- Develop verification testbench in IP/SOC level.
- Develop verification IP and reference model.
- Implement test with randomization-based coverage driven verification methodology.
- Implement functional and functional/code coverage closure.
- Hands-on code/debug with Verilog/SystemVerilog/UVM, and C/C++/SystemC.
- Verification automation flow based on Python/Perl.
- Cross Team and Cross site collaboration.
- Bachelor's Degree /Master's Degree in EEE/Computer/IC design.
- Strong ability on problem analyzing and solving, logic thinking and mindset.
- Quick to learn new language and technology.
- IC design or Verification knowledge (UVM, Verilog, Perl, Python, ARM SOC) is plus.
- Good teamwork.
ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area.
In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!
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Job Detail
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Job IdJD1210824
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationSingapore, Singapore
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EducationNot mentioned