Job Description

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The Opportunity

Adecco is partnering with a well-established Semiconductor company

Get to be involve with new technology project frequently

The Talent

Degree in Electrical and Electronic Engineering, Computer Engineering, IC Design or any related discipline

Good knowledge in analog layout fundamentals, such as floorplan, device matching, EM and IR

Possesses skills with Synopsys/ Cadence layout editor and verification tools (debugging DRC/LVS)

Familiar with UNIX Scripting with TCL, Perl or C-shell

The Job

At least 3 to 5 years with advance node (FinFET) process layout experience.

Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones

Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow

Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule

Responsible for in-house IP / library developments / Full chip integration

Next Steps

Prepare your updated resume (please include your current salary package with full breakdown such as base, incentives, annual wage supplement, expected package and reason for leaving.)

To apply online, please click on the link and contact us to follow-up. Alternatively, please send your resume to technicalstaffing@adecco.com .

All shortlisted candidates will be contacted. All the best!