Job Description

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The company is top leading developer of integrated circuit to create energy-efficient semiconductor solutions for IoT endpoint devices.
Responsibilities
Design, verify and implement modules and/or subsystems used within the SoC designs.
Use verilog design language and implement the development with the Cadence tool suite.
Verification development will include creation, enhancement and maintenance of system verilog and UVM based test benches, supporting a wide variety of test stimulus and design abstraction levels (RTL/Gates/Models/FPGA).
Implementation of modules and design will include RTL synthesis and DFT insertion of digital designs at module, subsystem and system level, and timing analysis using STA tools in multiple modes of operation.
Develop, verify and support DFT functions within the system.
Requirements:
Demonstrated ability to develop and track realistic schedules, provide status reports, track and resolve issues is critical.
Experience in all aspects of the RTL to silicon flow and have led teams in this area previously, specifically in the areas of RTL design, verification and implementation.
Detailed knowledge of DFT design and deployment to production.
Knowledge and experience developing verilog based RTL modules to be used within a larger SoC.
Experience using advanced node rules, including power and testability support/optimization.
Knowledge and experience with Synthesis tools/flows, including STA (static timing analysis), LEC, and CPF based designs.
Knowledge and experience with C coding.
Knowledge and experience with verification techniques and metrics, including coverage, assertions, RTL and gate level simulations, SDF annotations and general test plan generation and test case development using C, verilog, or UVM.
Knowledge and experience with asynchronous, low power and multi-power domain techniques.
Knowledge and experience with SDF based simulations and debug.
Knowledge and experience using Linux based tools and scripting languages including git, perl, make, TCL and python.
Experience with low power and analog design is preferred but not required.
Next Step:
Interested applicants, please send your resume to kevin.yeoh@adecco.com with your current and expected salary.
All shortlisted candidates will be contacted.
Kevin Yeoh Cia Hau
Direct Line: +65 6697 7806
EA License No: 91C2918
Personnel Registration Number: R1766290
Multinational Company
Permanent Role
Company Expansion