Job Description

:

• Derive specs and implement necessary customized and highly efficient building blocks such as systolic array, data path controller, scheduler, integer and floating-point processing engine, FFT, etc which are frequency used in various computing architecture such as in-memory computing, deep learning and neuromorphic computing.
• Model, evaluate and optimize digital and mixed-signal hardware accelerator.
• Develop (both front-end and back-end) compact, low-power digital block IP.
• Perform back-end floor planning, power planning, placement, clock-tree synthesis, timing closure and post-layout simulation of various digital and mixed-signal blocks/systems.
• Work with a cross-functional engineering team to perform algorithm/firmware/hardware co-design & co-optimization to achieve trade-offs among performance, cost and power, for various Artificial Intelligence (AI) related platform development, especially analog computing.
• Test and verify fabricated chip using FPGA and other lab equipment such as logic analyzer and oscilloscope.
• Publish research works in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II.

Job Requirements:

• PhD/master\'s degree in electrical engineering, Computer Engineering or related field
• With 2 years of experience
• Strong expertise in low power/custom digital circuit design
• Strong background and experience in digital back-end flow
• Familiar with system prototype using FPGA
• Solid background in system modeling and verifications
• Strong team work ethic and good interpersonal skills

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.
Type of Employment : Full-Time
Minimum Experience : 2 Years
Work Location : Fusionopolis