Job Description

Position description

Posting title

Senior/Staff ME/BE Digital Design Engineer (Ref: 2023-31111)

Regular/Temporary

Regular

Contract duration (nb of months)

0

Job description

About MDG:
Microcontrollers & Digital ICs Group (MDG) contributes to many of ST\xe2\x80\x99s strategic goals for Industrial, Personal Electronics and Communications Equipment. MDG represents about one third of ST\xe2\x80\x99s business. MDG is the world\'s leading manufacturer of microcontrollers and a leader in embedded SIM cards and EEPROM. It\xe2\x80\x99s focuses on the market for contactless NFC products and RF mixed signal technologies. MDG represents around 3000 employees (mainly R&D teams in France) located in 40 countries, with a revenue of above 3 billion dollars in 2020. It is addressing 2 major activities: the General-Purpose Microcontroller subgroup, the Connected Security sub-group, which covers products based on non-volatile memory technology and accounts for about 80% of MDG\'s revenue. Then, the Radio Frequency and Communication sub-group, which focuses on RF, Digital & Mixed Signals activities, representing about 20% of MDG activities.


About Connected Security:
In the fast-growing digital world, STSECURE products and solutions protect your privacy and your assets by ensuring their confidentiality, their integrity, and their availability to authorized requesters where and when needed. We deliver hardware- and software-certified solutions, offer seamless integration of security features, and are experts in cryptography and device architecture. With its STSECURE portfolio, ST is securing all your applications from traditional applications, such as SIM, banking, and ID, to the latest ones including contactless transactions and IoT connectivity.
The position is an exciting opportunity to be part of a dynamic team in the growing markets of secure microcontrollers used in state-of-the-art secure applications including IOT, Mobile, Banking and Band Protection. The role works within the physical digital team in Singapore that includes all disciplines required for physical design & verification.


Work Location: 5A Serangoon North Avenue 5 Singapore 554574


Job scope:

• Responsible for SOC level RTL to GDS implementation
  • Physical Synthesis
• • Develop timing constraints.
  • Hierarchical UPF flow
  • Static Timing and Crosstalk Analysis to ensure ensure timing closure of full design.
  • Formal verification
  • Physical design implementation, multi-power domain floor planning, power planning, MMMC scenarios Place and Route, clock tree synthesis, and physical verification
• Schedule preparation and execution adhere to plan.
• Good reporting to the management.

Profile

Requirements:

• Bachelor\xe2\x80\x99s/ Master\xe2\x80\x99s in Electronics Engineering with at least 5 years\xe2\x80\x99 experience in physical design and verification.
• Familiar with hierarchical physical design strategies, methodologies, and deep sub-micron technology.
• Proficient in Synthesis and STA.
• Proficient in constraints development interacting with RTL and DFT teams.
• Hands-on experience on multi-power domain designs
• Experience in low power physical design, floor planning and partitioning, congestion analysis, placement optimization, clock-tree synthesis, and timing closure.
• Proficient in programming/scripting with good coding experience in Tcl/Perl/Python.
• Good communication and written skills in English.
• Able to work in a multi-cultural team.
• Strong analytical and problem-solving skills
• Hands-on experience with leading EDA tools (such as Synopsys IC Compiler, Primetime, and Cadence Innovus) in physical implementation flow is mandatory.
• Good knowledge on EM/IR-Drop/crosstalk analysis (Redhawk), formal or physical verification will be an advantage.

Position location

Job location

Asia-Pacific, Singapore, Ang Mo Kio
Candidate criteria

Education level required

4 - Bachelor degree

Experience level required

6-10 years

Languages

English (2- Business fluent)
Requester

Desired start date

02/05/2023