Job Description

. Design-Technology Co-Optimization (DTCO) for RRAM and MRAM-based memory circuit and architecture design. . Memory DOE development including bit cell, array, read/write circuit design, layout and te . Design-Technology Co-Optimization (DTCO) for RRAM and MRAM-based memory circuit and architecture design. . Memory DOE development including bit cell, array, read/write circuit design, layout and test automation. . Memory architecture development, including energy efficient memory macro and novel Compute-In-Memory design concept. Memory compiler development experience is a plus. . Perform architecture level to evaluate the impact of new memory cell/circuit/macro design for domain-specific architectures such as AI hardware. . Familiar with basic digital design flow (design specification, design capture in RTL, back-end implementation, and mixed-mode chip integration) is a plus. . Work with a cross-functional engineering team to perform algorithm/firmware/hardware co-design & co-optimization to achieve trade-offs among performance, cost and power, for various Artificial Intelligence (AI) related platform development, especially analog computing. . Publish research work in prestigious conferences and Journals such as ISSCC, VLSI Symp, A-SSCC, DAC, JSSC and TCAS-I/II. Job Requirements . PhD holder with excellent track record of publications . 3-5 years of experience . Strong background and experience in memory circuit design (memory cell, sense amplifier, reference voltage generator etc), memory architecture and custom digital/mixed signal circuit designs (leakage-suppressed logic gates and DFF). . Experience in layout and implementation in advanced nodes such as 28nm CMOS and below. . Good understanding of CMOS device behavior and characterization is a plus. . Relevant background in rtl and pnr is a plus.