Sr/ Ic Design Engineer (design Verification)
SG, Singapore
Job Description
s
Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matrix using cover point and assertion Create and debug tests for DUT Resolve bugs with remote designers
Requirements
Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM Strong understanding of verification process from test plan to coverage completion Strong communication and Analytical skills Understanding of HDL (Verilog, VHDL) * Experience in using leading EDA software tools like Cadence/ Synopsys
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Job Detail
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Job IdJD1609777
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationSG, Singapore
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EducationNot mentioned