Job Description

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• Lead, drive and execute Standard cell characterization, QA flows and its methodology development, deliver library view generation to enable digital, analog and mixed signal design and PnR flows

• Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics. Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.

• Develop and execute test plans for standard cell library characterization, including timing, power, noise, and reliability analyses. Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.

• Perform detailed analysis of characterization data, identify deviations and anomalies, and propose corrective actions. Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.

• Collaborate with the design automation team to enhance characterization methodologies and develop automation scripts for efficient library characterization. Participate in technology node evaluations and provide recommendations for standard cell library optimizations based on technology roadmaps.

• Collaborate with product development teams to ensure smooth integration and validation of standard cell libraries in advanced chip designs. Stay up-to-date with the latest advancements in FinFET technology, standard cell design methodologies, and industry trends.

• Bachelor\xe2\x80\x99s or Master\xe2\x80\x99s degree in Engineering with a minimum of 10 years of experience in standard cell design. This includes setting up library characterization flows and methodologies, QA flows, circuit design, layout, and simulation, with a strong emphasis on FinFET technologies (e.g., 16nm, 12nm, 6nm, or below).

• Proficient in defining, characterizing, and executing custom digital and analog cells, low power management cells, level shifters, retention flops, GPIOs, and memories.

• Expertise in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence Virtuoso Liberate/LV/Mx/Trio, Virtuoso, ADE, Genus, Innovus and Tempus.

• Solid understanding of FinFET technology and its impact on standard cell library design and characterization. Experience in characterizing standard cell libraries for advanced process nodes is highly desirable.

• Knowledge of standard cell architecture, design rules, and layout considerations. Familiarity with circuit and layout design, static timing analysis (STA), Physical design and power analysis methodologies.

• Strong analytical skills and attention to detail for data analysis and problem-solving.

• Excellent programming and scripting skills (e.g., Python, Perl, Tcl) for automation and data processing tasks.

• Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.

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