Job Description

Purpose of the Job:

To support R&D activities for 2.5D wafer-level packaging (WLP) processes--including Die Preparation, Chip Attach, and Mold--focusing on process reliability, manufacturability, and integration for advanced semiconductor packages.

Key Job Accountabilities:

Develop and optimize key 2.5D CoW (Chip-on-Wafer) processes: Die Preparation: grinding, laser grooving, dicing saw Chip Attach: TCB (Thermo-Compression Bonding), LCB (Laser Compression Bonding) Mold: compression or transfer mold for warpage and protection Perform material evaluation and reliability analysis (e.g., XRF, shear test) Conduct DOE/FMEA for robust process design and improvement Work closely with cross-functional teams (e.g., Bumping, RDL, Failure Analysis) to enable seamless process integration Track and analyze industry trends in equipment, materials, and technologies Support new product introduction (NPI) and yield ramp-up through structured problem-solving Document process flows, risk assessments, and engineering reports

Scope of the Job:

Directly impacts production readiness, yield, and reliability of high-value 2.5D packages Supports NPI for advanced semiconductor customers (e.g., AI, HPC, and memory applications) Influences supplier qualification and capital decisions related to 2.5D tooling and materials Contributes to revenue generation through early ramp-up and stable process delivery

Required Experience and Qualifications:

Bachelor's degree or higher in Engineering (Materials, Electronics, Chemical, Mechanical, or related field) 3+ years of hands-on experience in semiconductor packaging process development (Die Prep, Chip Attach, or Mold) Proficient in DOE, FMEA, statistical process control, and failure analysis Familiar with process and reliability evaluation tools (e.g., XRF, shear test, SAM) Skilled in documentation and cross-functional communication * Experience in OSAT, Fab, or advanced packaging (e.g., 2.5D/3D, HBM, interposer) (Preferred)