Job Description

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. JR37953 INTERN - PROCESS INTEGRATION Location : 1, North Coast Drive, Singapore 757432 Department : Product Integration Engineering (PIE)

Project Title: Process characterization and recipe optimization for metal interconnect structural failures in 3D NAND CMOS Under Array (CuA) architecture

Description: 3D NAND memory scaling is achieved through stacking more memory layers vertically. It also requires peripheral circuitry shrink within CuA design to produce smaller die size with higher density. This results in tighter process margin for the peripheral metal interconnect structure, causing multiple structural failures which affect product yield and quality. In this project, students will be exposed to complex processes that create the CuA structures in 3D NAND and obtain first hand experience in process integration, recipe development, structural characterization, and process control methodology used in wafer fabrication.

Scope: Perform process characterization on defective CuA metal interconnect structures to understand the root cause and comprehend interaction between series of process steps involved in the structure formation. Collaborate with process engineers to explore process recipe optimization opportunity to mitigate the fails and reduce process variability. Students will be exposed to perform Design of Experiment (DoE) methodology based on characterization data collected. Students will also be able to learn how to use statistical tools and fab-specific software for operation and trouble-shooting purpose.

Deliverables: Characterization data on defective metal interconnect structure and interaction among process steps. Develop Best Known Method to optimized and reduce process variability through DoE and data analysis.

Skillset Required :

• Students pursuing Bachelor\'s degree in engineering,

Course of interests :

• Engineering

Duration Period :

• 6 months

About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron\xc2\xae and Crucial\xc2\xae brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities \xe2\x80\x94 from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_sg@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.