Job Description

Key Responsibilities:

Work closely with design team and make sure DFT structures are correctly inserted. Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs. Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault model Responsible for debugging of scan/mbist pattern issues on bench/ATE to root cause the problem Assist in Diagnosis and Yield enhancement through product lifecycle

Qualifications:

BS or MS in Electrical/Electronic/Computer Engineering with 3 or more experience as DFT engineer Experience in creating and implementing complex chip-level DFT architecture Experience in DFT implementation including Scan and Scan Compression at IP and SoC level Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression. Proficient in logic design using Verilog and experience in synthesis and STA Experience in developing test benches and simulation in RTL/GATE/SDF environments Knowledge of MBIST is a plus. Knowledge of FPGA synthesis and design flow is a plus Experience with post-silicon debug and bench setup is a plus Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, Python etc Good communication skills, self-motivated, works well in a group environment that spans across continents



Ethos Search Associates Pte. Ltd.


EA License No: 13C6655


EA Reg No: R1988580 Jacky Chong